The present invention generally relates to gate arrays, and more particularly to a gate array which effectively utilizes an interconnection (wiring) region.
The demand for the gate arrays is increasing due to the fact that the gate array can be used to develop a semi-customized semiconductor integrated circuit at a relatively low cost within a short time. At the same time, there are much demands on the gate array to realize multiple functions and high integration density. For this reason, there is a need to effectively utilize the interconnection region of the gate array.
FIG. 1 is a plan view generally showing a conventional gate array. The gate array comprises a chip (substrate) 10 which is constituted by a silicon wafer or the like, and basic cell columns 11 are arranged parallel to each other with predetermined intervals on the chip 10. Each basic cell column 11 is made up of a plurality of basic cells 14. Two mutually adjacent basic cell columns 11 are separated by an empty region of a predetermined width, that is, an interconnection region 12. The interconnection region 12 is primarily provided for the purpose of forming an interconnection wiring layer which connects the basic cell columns 11. A plurality of input/output cells 13 are provided on a peripheral portion of the chip 10. The input/output cells 13 are provided to form an interface between a circuit formed within the chip 10 and an external circuit.
Each of the basic cells 14 constituting the basic cell column 11 may have a structure shown in FIG. 2. In FIG. 2, a basic cell 14A comprises two parallel gate electrodes 15 and 16 extending in a direction perpendicular to the basic cell column 11, and a p-type diffusion region 17 and an n-type diffusion region 18 for forming respective source regions and drain regions of p-channel transistors P1 and P2 and n-channel transistors N1 and N2 having the gate electrodes 15 and 16. Hence, a first transistor pair is made up of the p-channel transistor P1 and the n-channel transistor N1 having the gate electrode 51 in common, and a second transistor pair is made up of the p-channel transistor P2 and the n-channel transistor N2 having the gate electrode 52 in common. As shown in FIG. 2, each of the transistors P1, P2, N1 and N2 have a channel width W and a channel length L. In other words, a channel width-to-length ratio is W/L for each of the transistors P1, P2, N1 and N2.
In the conventional gate array shown in FIG. 1, the circuit on the chip 10 is constituted by the basic cells 14 having the structure shown in FIG. 2. For this reason, in a case where a driving capacity of the transistors constituting the basic cells 14 is too small, it is necessary to use a plurality of basic cells 14 so as to obtain equivalents of transistors having a large channel width-to-length ratio.
As one example of the case where the driving capacity of the transistors constituting the basic cells 14 is too small, there is a case where a bus driver is to be constituted by a transmission gate. The transmission gate functions as a switch for forming a connection and a disconnection between a bus line and a driver, and it is essential that a signal delay time is kept down to a minimum. For this reason, the channel width-to-length ratio of the transistors constituting the transmission gate is set to a sufficiently large value, so as to reduce the resistance when the transmission gate is turned ON. Normally, a channel width-to-length ratio which is two to three times that of the transistors constituting the basic cell 14A shown in FIG. 2 is required for the transistors constituting the transmission gate. As a result, a plurality of basic cells 14 are connected in parallel to constitute the transmission gate.
As will be described later, in a case where basic circuit blocks belonging to different basic cell columns 11 are connected by a bus line, a bus driver is provided between an output of the basic circuit block and the bus line. Generally, the bus driver comprises a driver circuit 25 and a transmission gate 26 as shown in FIG. 4, and the bus driver is provided between a basic circuit block 24 and a bus line 27. The transmission gate 26 is made up of a p-channel transistor Q.sub.p and an n-channel transistor Q.sub.n. The transmission gate 26 is controlled to a conductive state and a non-conductive state depending on control signals CNT and CNT applied to respective gates of the transistors Q.sub.p and Q.sub.n, thereby connecting and disconnecting the basic circuit block 24 to and from the bus line 27.
However, the transistors constituting the basic cell 14A shown in FIG. 2 have in common one of the gate region, the drain region and the source region. Consequently, predetermined transistors are ineffective and unused when the plurality of basic cells 14 are connected in parallel to constitute the transmission gate.
In other words, two driver circuits 25 can be made from one basic cell 14A, however, only one transmission gate 26 can be made from one basic cell 14A because the p-channel transistor Q.sub.p and the n-channel transistor Q.sub.n must have independent gates. Hence, if the p-channel transistor P1 and the n-channel transistor N2 shown in FIG. 2 were used to constitute the transmission gate 26, the p-channel transistor P2 and the n-channel transistor N1 are ineffective and unused.
Accordingly, in a circuit having a plurality of bus drivers built therein, there is a problem in that the deterioration in the utilization efficiency of the chip area due to the ineffective transistors cannot be neglected.
On the other hand, the structure of the basic cells 14 may be changed as shown in FIG. 3 so that the transmission gate may be constituted thereby. A basic cell 14B shown in FIG. 3 comprises a p-type source/drain region 20 which is formed by injecting impurities into the chip 10, an n-type source/drain region 21 formed by injecting impurities into the chip 10, and gate electrodes 22 formed on the source/drain regions 20 and 21 and extending in a direction perpendicular to the basic cell columns 11. Hence, the basic cell 14B comprises at least one pair of p-channel transistors and one pair of n-channel transistors.
In the example shown in FIG. 3, a pair of p-channel transistors are constituted by the p-type source/drain region 20 and two independent gate electrodes 22a and 22b of the gate electrodes 22, and a pair of n-channel transistors are constituted by the n-type source/drain region 21 and two independent gate electrodes 22c and 22d of the gate electrodes 22. In other words, first and second transistor pairs are formed, where each transistor pair is made up of a p-channel transistor and an n-channel transistor. In FIG. 3, CA denotes contact regions for supplying a predetermined voltage to the semiconductor substrate on which the transistors are formed or to a well.
Normally, the basic cells 14 within the same basic cell column 11 are used to form a basic circuit block constituted by logic circuits such as a NAND circuit and a NOR circuit. The basic circuit blocks belonging to different basic cell columns 11 are connected to form one integrated circuit on the chip 10. The interconnection for connecting the basic circuit blocks is formed in the interconnection region provided between the basic cell columns 11.
In a case where the basic circuit blocks belonging to different basic cell columns 11 are connected by a bus line, a bus driver is provided between an output of the basic circuit block and the bus line. Generally, the bus driver comprises the driver circuit 25 and the transmission gate 26 as described before in conjunction with FIG. 4, and the bus driver is provided between the basic circuit block 24 and the bus line 27.
When producing an integrated circuit by use of the normal gate array, the driver circuit 25 and the transmission gate 26 of the bus driver are constituted by the basic cells 14B shown in FIG. 3, for example, and FIG. 5 shows an example of the conceivable interconnection for forming the transmission gate 26 by the basic cells 14B. In FIG. 5, a bold solid line and a bold phantom line denote a lower interconnection L1 and an upper interconnection L2, respectively. The lower interconnection L1 connects through contact holes 30 to the p-type source/drain region 20, the n-type source/drain region 21, the gate electrodes 22 and the contact regions CA. On the other hand, the upper interconnection L2 connects to the lower interconnection L1 through through holes 31 formed in an insulating layer (not shown) provided between the upper and lower interconnections L2 and L1. The upper interconnection L2 constitutes leader lines for an input line IN and an output line OUT of the transmission gate 26. In FIG. 5, the contact holes 30 are indicated by circular marks, and the through holes 31 are shown as double circular marks.
Normally, the two p-channel transistors within the basic cell 14B are connected in parallel and the two n-channel transistors within the basic cell 14B are similarly connected in parallel as shown in FIG. 5, to thereby constitute the transmission gate 26.
The interconnections L1 and L2 are arranged on predetermined imaginary grids so as to automatically design the interconnection arrangement by the CAD technique. In FIG. 5, the basic cell 14B occupies grid numbers "1" to "10" running parallel to the basic cell column 11. The lower interconnection L1 is connected to the transistors within the basic cell 14B through the contact holes 30 arranged on these grids.
It is desirable that the through hole 31 provided for connecting the interconnections L1 and L2 is not located above the contact hole 30 provided for connecting the lower interconnection L1 to the transistors. For this reason, the through hole 31 is formed on a grid which is different from the grid on which the contact hole 30 is formed. In addition, an element isolation region amounting to approximately one grid interval is provided between the p-channel transistors and the n-channel transistors in FIG. 5.
Therefore, the following problems occur in the arrangement shown in FIG. 5.
Firstly, it is necessary to provide the interconnections in two levels, because the leader line (that is, the upper interconnection L2) for the input line IN and output line OUT of the transmission gate 26 intersects the lower interconnection L1 which makes internal connections within the basic cell 14B.
Secondly, the contact holes 30 and the through holes 31 are arranged parallel to the basic cell column 11 over a large distance of nine grid intervals in FIG. 5.
Thirdly, the lower interconnection L1 is arranged to make the internal connections within the basic cell 14B over a large distance of four grid intervals of the grids running perpendicularly to the basic cell column 11 in FIG. 5.
In other words, the number of grids over which the connections are made to constitute the transmission gate 26 is large, and consequently, a degree of freedom with which the interconnection may be designed to connect the basic circuit blocks is small. In addition, the necessity to provide the interconnections in two levels makes the process of forming the interconnection complex. Hence, it is desirable that the interconnection can be made over a small number of grids, and it is also desirable to avoid the interconnections in two levels.